1. Field of the Invention
The present invention relates to an analog signal amplifying circuit, and more particularly to a technique effective for a use for lowering the capacity of an output capacitor of an image signal amplifying circuit having prescribed output impedance on the side of outputting a signal and prescribed input impedance on the side of receiving a signal.
2. Related Art
For example, a circuit shown in FIG. 4A is known as an amplifier circuit for amplifying an image signal read from a digital versatile disc (DVD) or the like and converted by digital to analog (DA) conversion, and for outputting the amplified image signal to a television apparatus or the like through a cable. This kind of the image signal amplifying circuit uses an output capacitor C1 for transmitting only the alternating current component of the image signal, and for example, the Japan Electronics and Information Technology Industries Association (JEITA) prescribes each of the resistance values of both of a resistance R1 connected to the output capacitor C1 in series with each other and an input resistance Ri of the side of the input equipment for receiving the output image signal to 75Ω. Consequently, the load viewed from a buffer on the side of the output equipment is 150Ω in total.
Now, because an image signal is a signal having a very wide frequency range such as the one from 30 Hz to 6 MHz, if the amplifier circuit configured as shown in FIG. 4A is used for amplifying the image signal, then the output capacitor C1 and the resistances R1 and Ri constitute a high pass filter, and it is required to set the cut-off frequency thereof to about 1 Hz in order to output an image signal of 30 Hz without any distortion. In this case, because the output capacitor C1 is required to have a large capacitance value such as 1000 μF, it is obliged to use an electrolytic capacitor as the output capacitor C1, and the use of the electrolytic capacitor has been a cause of preventing the cost reduction and miniaturization of the output capacitor C1.
Accordingly, a technique for enabling the miniaturization of the output capacitor C1 while preventing the occurrence of a sag, which is the hanging of the waveform of an output signal, by connecting a feedback capacitor C2 and a resistance R2 between the output terminal and the negative phase input terminal of an operational amplifier AMP1 as shown in FIG. 4B was developed. The circuit shown in FIG. 4B has an advantage of being capable of reducing the capacitance value of the output capacitor C1 to about 1/10 of that of the circuit shown in FIG. 4A. The circuits shown in FIGS. 4A and 4B are disclosed in, for example, FIGS. 3C and 3B, respectively, of Japanese Patent Application Laid-Open Publication No. 2004-274434 (hereinafter referred to as Patent Document 1) as related art.
The circuit shown in FIG. 4B has an advantage of being capable of setting the capacitance value of the output capacitor C1 to be about 1/10 of that of the circuit of FIG. 4A. However, the capacitance of the output capacitor C1 is needed to be about 100 μF even in this case, and the capacitance of the feedback capacitor C2 is needed to be about 22 μF. Consequently, it is needed to use electrolytic capacitors, which are relatively expensive, as the capacitors C1 and C2, and a problem of the difficulty of being unable to attain sufficient cost reduction remains.
Moreover, the circuit of FIG. 4B has a disadvantage that the input dynamic range thereof becomes narrow when the circuit is adapted to have a low power source voltage. The Patent Document 1 discloses an invention enabling the circuit to have a wide input dynamic range by using an inverting amplifier circuit. However, even in this invention, the output capacitor C1 is required to have the capacitance of about 100 μF, and the feedback capacitor C2 is required to have the capacitance of about 22 μF. Although, the invention enables the miniaturization of the capacitors C1 and C2 in comparison with the circuit of FIG. 4A, the invention cannot attain sufficient cost reduction similarly to the circuit of FIG. 4B.
Moreover, since the invention of the Patent Document 1 uses the inverting amplifier circuit, the invention has a disadvantage of the inversions of image signals. In order to avoid the disadvantage, the invention is required to provide another inverting amplifier circuit at the preceding stage of the inverting amplifier circuit as disclosed in FIG. 5 of the Patent Document 1, and then the invention has a problem of causing the further enlargement of the circuit size thereof.
On the other hand, as an invention enabling further miniaturization of the capacitor while preventing the occurrence of any sag by using a non-inverting amplifier circuit, for example, there is an invention disclosed in Japanese Patent Application Laid-Open Publication No. 2005-184056 (hereinafter referred to as Patent Document 2). The invention is provided with a low pass filter 6, which extracts a direct-current component from an output image signal of an amplifier 4, and an adding circuit 5 as shown in FIG. 5, and inputs the input image signal including the added direct-current component into the amplifier 4. Thus the invention corrects the sag occurred in the high pass filter on the output side. Consequently, the invention of the Patent Document 2 has a similar problem and an object to those of the present invention and enables the miniaturization of the capacitor to the same degree as that of the present invention, but the object resetting method of the invention of the Patent Document 2 is greatly from that of the present invention.